报告题目：Hardware-Software Co-design for Point-to-Point Network-on-Chip based Many-Core Systems
报告人：Weichen Liu（刘韦辰）, Nanyang Technological University（南洋理工大学）
时间：2023年5月30日 （周二）下午3:00 - 4:00
With the increasing number of processing elements (PEs) integrated into a chip, the communication between the PEs becomes the performance bottleneck. Network-on-Chip (NoC) is a popular on-chip communication paradigm that can connect a large number of PEs thanks to its high scalability and efficiency. Nevertheless, the performance of such communication backbone is limited by two issues. First, hop-by-hop transmission results in time-consuming long-distance communication, especially when the network size grows. Second, improper resource management strategies cause unnecessary network contentions, which results in huge delay and drastically degrades the NoC performance, especially when the communication volume increases. To address these challenges, we propose a software and hardware collaborated methodology to design a novel NoC. (1) We propose (1) a software-defined point-to-point NoC architecture, ArSMART, enabling arbitrary packet routing and application-specific communication optimization, (2) a method to co-optimize task mapping and routing to accelerate computation and communication simultaneously, extending ArSMART to heterogeneous systems, and (3) a technique for parallel multipath transmission to fully utilize the parallelism in NoCs, further reducing transmission latency in ArSMART. The holistic design can effectively boost the NoC performance in application-specific many-core systems.
Weichen Liu is an Associate Professor at the School of Computer Science and Engineering, Nanyang Technological University, Singapore. He was a Nanyang Assistant Professor (NAP) during 2018-2023. He received his PhD degree from the Hong Kong University of Science and Technology, and the MEng and BEng degrees from Harbin Institute of Technology, China.
Dr. Liu serves as an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), and a Subject Area Editor of Elsevier Journal of Systems Architecture (JSA). He served as a General Chair of the 25th IEEE International Symposium on Real-Time Computing (ISORC 2020), a Program Chair of ISORC 2019, a Track Chair of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2021, 2022), The 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2023), and a chair, technical program committee member, organizing committee member and guest editor of over 20 premier international conferences, journals, workshops and student forums, including DAC, ICCAD, ASP-DAC, CODES+ISSS, RTSS, RTAS, ISLPED, GLSVLSI, MSC@ESWEEK, SRF@ASP-DAC, EAI@ICDCS, etc.
Dr. Liu authored and co-authored more than 170 research papers in peer-reviewed journals, conferences and books, and received the best paper candidate awards from ISLPED 2023, DATE 2023, GLSVLSI 2022, ASP-DAC 2020, 2019 and 2016, CASES 2015, CODES+ISSS 2009, and the best poster paper awards from SRF@ASP-DAC 2020 and 2017, RTCSA 2017, AMD-TFE 2010. His research was supported by leading industrial partners including Intel, AMD, Xilinx, MediaTek, Huawei and HP.